library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity pwm_demo is
	port (
		clock: in std_logic;
        reset: in std_logic;
		direction: in std_logic;
		dutycycle: in std_logic_vector(9 downto 0);
		pwm_out: out std_logic;
		direction_out: out std_logic
	);
end pwm_demo;

architecture arch_pwm of pwm_demo is
	signal counter : unsigned(9 downto 0);
begin

	seq: process(clock, reset)
	begin
        if (reset='1') then
			counter <= (others => '0');
			pwm_out <= '0';
		elsif (rising_edge(clock)) then
			if (counter < unsigned(dutycycle)) then
				pwm_out <= '1';
			else
				pwm_out <= '0';
			end if;
			counter <= counter + 1;
		end if;
	end process;
	
	direction_out <= direction;
end arch_pwm;
